{"id":615,"date":"2008-09-08T16:32:37","date_gmt":"2008-09-08T16:32:37","guid":{"rendered":"http:\/\/pchero21.com\/?p=615"},"modified":"2008-09-08T16:32:37","modified_gmt":"2008-09-08T16:32:37","slug":"avr-%eb%a7%88%ec%9d%b4%ed%81%ac%eb%a1%9c%ec%bb%a8%ed%8a%b8%eb%a1%a4%eb%9f%ac-%ec%9e%85%ec%b6%9c%eb%a0%a5-%ed%8f%ac%ed%8a%b8-%ed%8a%b9%ec%a7%95","status":"publish","type":"post","link":"http:\/\/pchero21.com\/?p=615","title":{"rendered":"AVR \ub9c8\uc774\ud06c\ub85c\ucee8\ud2b8\ub864\ub7ec \uc785\ucd9c\ub825 \ud3ec\ud2b8 \ud2b9\uc9d5"},"content":{"rendered":"

 * AVR \ub9c8\uc774\ud06c\ub85c\ucee8\ud2b8\ub864\ub7ec \uc785\ucd9c\ub825 \ud3ec\ud2b8 \ud2b9\uc9d5<\/p>\n

 – 6\uac1c\uc758 8\ube44\ud2b8 I\/O \ud3ec\ud2b8\uc640 1\uac1c\uc758 5\ube44\ud2b8 I\/O \ud3ec\ud2b8\ub85c \uad6c\uc131\ub418\uc5b4 \uc788\ub2e4.
 – \ucd9c\ub825\ud3ec\ud2b8\uc758 \ubc84\ud37c\ub294 \ub9ce\uc740 \uc720\uc785\uc804\ub958\uc640 \uc720\ucd9c\uc804\ub958\ub97c \uc0ac\uc6a9(\ucd5c\ub300 40mA)\ud560 \uc218 \uc788\ub2e4.
 – \ubaa8\ub4e0 \ud3ec\ud2b8 \ud540\uc740 \uac1c\ubcc4\uc801\uc73c\ub85c \ub0b4\ubd80 \ud480\uc5c5 \uc800\ud56d\uc744 \uc0ac\uc6a9\ud560 \uc218 \uc788\ub2e4.
 – \ubaa8\ub4e0 I\/O\ud540\uc740 VCC\uc640 GND \uc0ac\uc774\uc5d0 \ub2e4\uc774\uc624\ub4dc\ub97c \uc811\uc18d\ud558\uc5ec \ud3ec\ud2b8\ub97c \ubcf4\ud638\ud55c\ub2e4.
 – Read-Modify-Write\uae30\ub2a5\uc744 \uac00\uc9c0\uace0 \uc788\uc5b4, \ube44\ud2b8 \ub2e8\uc704\uc758 \ud3ec\ud2b8 \uc124\uc815\uc774 \uc790\uc720\ub86d\ub2e4.
 – \uac01 \ud3ec\ud2b8\uc5d0 \ub300\ud55c \ub370\uc774\ud130 \ucd9c\ub825\uc6a9 \ub808\uc9c0\uc2a4\ud130(PORTx)\uc640 \ub370\uc774\ud130 \uc785\ucd9c\ub825 \ubc29\ud5a5 \uc9c0\uc815\uc6a9 \ub808\uc9c0\uc2a4\ud130(Data Direction Register : DDRx), \uadf8\ub9ac\uace0 \uc785\ub825\uc6a9 \ub808\uc9c0\uc2a4\ud130 (PINx)\ub97c \uac00\uc9c0\uace0 \uc788\ub2e4.<\/p>\n

 * AVR \ub9c8\uc774\ud06c\ub85c\ucee8\ud2b8\ub864\ub7ec\ub294 \uc785\ucd9c\ub825 \ud3ec\ud2b8\ub97c \uc81c\uc5b4\ud558\uae30 \uc704\ud574\uc11c, DDxn, PORTxn, PINxn\uc758 3\uac1c\uc758 \ub808\uc9c0\uc2a4\ud130\ub97c \uc0ac\uc6a9\ud55c\ub2e4.<\/p>\n

 * DDRx \ub808\uc9c0\uc2a4\ud130
 – \uc785\ucd9c\ub825\uc758 \ubc29\ud5a5\uc124\uc815\uc744 \ud558\uae30 \uc704\ud55c \ub808\uc9c0\uc2a4\ud130\uc774\ub2e4. DDRA ~ DDRG \ub808\uc9c0\uc2a4\ud130\uc758 \uc785\ucd9c\ub825\ud3ec\ud2b8\uc5d0 \ub300\uc751\ud558\ub294 \ud574\ub2f9 \ube44\ud2b8\uc5d0 1\uc744 \uc4f0\uba74 \uadf8 \ud574\ub2f9 \ud540\uc774 \ucd9c\ub825\uc73c\ub85c, 0\uc744 \uc4f0\uba74 \uc785\ub825\uc73c\ub85c \uc124\uc815\ub41c\ub2e4. \ucd08\uae30\uac12\uc744 0\uc73c\ub85c \uc124\uc815\ub418\uc5b4 \uc788\ub2e4. \ube44\ud2b8\ubcc4\ub85c \ub9cc\uc57d \ud3ec\ud2b8 A\uc758 \ube44\ud2b83\ub97c \ucd9c\ub825\uc73c\ub85c \uc124\uc815\ud558\ub824\uba74 DDRA = 0x08\ub85c \ud558\uba74 \ub418\uace0, \ud3ec\ud2b8 A\ub97c \uc804\ubd80 \ucd9c\ub825\uc73c\ub85c \uc124\uc815\ud558\ub824\uba74 DDRA = 0xff\ub85c \ud558\uba74 \ub41c\ub2e4.<\/p>\n

 * PORTx \ub808\uc9c0\uc2a4\ud130
 – \ub370\uc774\ud130\ub97c \ucd9c\ub825\ud558\uae30 \uc704\ud55c \ub808\uc9c0\uc2a4\ud130\uc774\ub2e4. DDRx\uc758 \uac12\uc744 \uc138\ud305\ud558\uc5ec \ucd9c\ub825\uc73c\ub85c \uc124\uc815\ub41c \uacbd\uc6b0 \ucd9c\ub825\uc744 \uc6d0\ud558\ub294 \ub370\uc774\ud130\uac12\uc744 PORTx \ub808\uc9c0\uc2a4\ud130\uc5d0 \ub123\uc5b4\uc8fc\uba74 \ub41c\ub2e4. PORTx \ub808\uc9c0\uc2a4\ud130\ub294 \uc77d\uae30\uc640 \uc4f0\uae30\uac00 \ubaa8\ub450 \uac00\ub2a5\ud558\ub2e4. \ube44\ud2b8\ubcc4\ub85c \uc124\uc815\ud558\ub824\uba74 PORTx = 1\uc758 \ud615\ud0dc\ub85c \ud558\uba74 \ub41c\ub2e4( x\ub294 A ~ G). \ub9cc\uc57d \ud3ec\ud2b8 B\uc758 \ube44\ud2b83\uc5d0 1\uc744 \ucd9c\ub825\ud558\ub824\uba74 PORTB = 0x08\ub85c \ud558\uba74 \ub41c\ub2e4.<\/p>\n

 * PINx \ub808\uc9c0\uc2a4\ud130
 – \ub370\uc774\ud130 \uc785\ub825\uc6a9 \ub808\uc9c0\uc2a4\ud130\uc774\ub2e4. \uc785\ucd9c\ub825 \ud540\uc774 \uc785\ub825\uc73c\ub85c \uc124\uc815\ub41c \uacbd\uc6b0 PINx \ub808\uc9c0\uc2a4\ud130\uc5d0 \ud574\ub2f9\ud558\ub294 \uac12\uc744 \uc77d\uc73c\uba74 \ub41c\ub2e4. \ud574\ub2f9 \ud540\uc758 \uac12\uc744 \uc77d\uc5b4 \ub4e4\uc778\ub2e4. \uc77d\uae30\ub9cc \uac00\ub2a5\ud558\uba70 \uc4f0\uae30\ub294 \uae08\uc9c0\ub418\uc5b4 \uc788\ub2e4. \ube44\ud2b8\ubcc4\ub85c \uc77d\uc5b4 \ub4e4\uc774\ub824\uba74 PINx\ub97c \uc0ac\uc6a9\ud558\uba74 \ub41c\ub2e4. \ube44\ud2b8\ubcc4\ub85c \ub9cc\uc57d \ud3ec\ud2b8C\uc758 \ube44\ud2b83\uac12\uc744 \uc77d\uc5b4 \ub4e4\uc5ec led3\ub77c\ub294 \ube44\ud2b8\uac12\uc5d0 \ud560\ub2f9\ud558\ub824\uba74 led3 = (PINC & 0x08)\ub85c \ud558\uba74 \ub41c\ub2e4.<\/p>\n

 * ATMega128 \ub9c8\uc774\ud06c\ub85c\ucf58\ud2b8\ub864\ub7ec\ub294 6\uac1c\uc758 8\ube44\ud2b8 \uc785\ucd9c\ub825 \ud3ec\ud2b8\uc640 1\uac1c\uc758 5\ube44\ud2b8 \uc785\ucd9c\ub825 \ud3ec\ud2b8\ub85c \uad6c\uc131\ub418\uc5b4 \uc788\ub2e4. \ucd9c\ub825 \ud3ec\ud2b8\ub4e4\uc740 \uc784\ubca0\ub514\ub4dc \uc2dc\uc2a4\ud15c\uc744 \uc124\uacc4\ud560 \ub54c \uadf8 \uc6a9\ub3c4\uc5d0 \ub9de\uac8c \uc801\uc808\ud788 \uae30\ub2a5\uc744 \ubd80\uc5ec\ud558\uac8c \ub41c\ub2e4. \uc2dc\uc2a4\ud15c\uc5d0\uc11c \uc694\uad6c\ub418\ub294 \uae30\ub2a5\uc5d0 \ub530\ub77c \ub0b4\uc7a5\ud560 \uc8fc\ubcc0 \uc18c\uc790\ub4e4\uacfc \uc678\ubd80 \uc778\ud130\ud398\uc774\uc2a4\ub97c \uacb0\uc815\ud558\uace0, \uadf8 \uc8fc\ubcc0 \uc18c\uc790\uc640 \uc678\ubd80 \uc778\ud130\ud398\uc774\uc2a4\ub4e4\uc744 \ub9c8\uc774\ud06c\ub85c\ucee8\ud2b8\ub864\ub7ec\uc758 \uac01 \uc785\ucd9c\ub825 \ud3ec\ud2b8\uc5d0 \uc801\uc808\ud788 \ubc30\ubd84\ud558\uc5ec \uc5f0\uacb0\ud574 \uc8fc\uc5b4\uc57c \ud55c\ub2e4. \uc608\ub97c \ub4e4\uc5b4 UART \uc778\ud130\ud398\uc774\uc2a4\ub97c \ud544\uc694\ub85c \ud558\ub294 \uc678\ubd80 \uc778\ud130\ud398\uc774\uc2a4\ub294 \ud3ec\ud2b8 D\ub098 \ud3ec\ud2b8 E\uc758 UART \ud3ec\ud2b8\uc5d0 \uc5f0\uacb0\ud558\uba74 \ub418\uace0, PWM \uc81c\uc5b4\uac00 \ud544\uc694\ud55c \ubaa8\ud130\ub294 \ud3ec\ud2b8 B\uc758 PWM \ud3ec\ud2b8\uc5d0, AD\ubcc0\ud658\uc774 \ud544\uc694\ud55c \uc13c\uc11c\ub4f1\uc740 \ud3ec\ud2b8 F\uc758 ADC \ud3ec\ud2b8\uc5d0 \uc5f0\uacb0\ud558\uba74 \ub41c\ub2e4. \ub9cc\uc57d \uc678\ubd80\uc5d0 \ub300\uc6a9\ub7c9\uc758 \uba54\ubaa8\ub9ac\ub97c \ubd99\uc5ec\uc57c \ud55c\ub2e4\uba74 \ud3ec\ud2b8 A, \ud3ec\ud2b8 C, \ud3ec\ud2b8 G\uc5d0 \uc788\ub294 \uc678\ubd80 \uba54\ubaa8\ub9ac \uc5f0\uacb0 \ud3ec\ud2b8\ub97c \uc0ac\uc6a9\ud574\uc57c \ud55c\ub2e4.<\/p>\n

 * \ud3ec\ud2b8 A(PA7 ~ PA0 : \ud540 44 ~ 51)
 – \ub0b4\ubd80 \ud480\uc5c5 \uc800\ud56d\uc774 \uc788\ub294 8\ube44\ud2b8 \uc591\ubc29\ud5a5 \uc785\ucd9c\ub825 \ub2e8\uc790\ub85c\uc11c, \uc678\ubd80 \uba54\ubaa8\ub9ac\ub97c \ub458 \uacbd\uc6b0\uc5d0\ub294 \uc8fc\uc18c\ubc84\uc2a4(A7-A0)\uc640 \ub370\uc774\ud130\ubc84\uc2a4(D7-D0)\ub85c \uc0ac\uc6a9\ub41c\ub2e4. \uc774\ub54c \uc5b4\ub4dc\ub808\uc2a4 \ubc84\uc2a4\uc640 \ub370\uc774\ud130 \ubc84\uc2a4\ub97c \uad6c\ubd84\ud558\uae30 \uc704\ud574\uc11c\ub294 ALE \uc2e0\ud638\ub97c \uc0ac\uc6a9\ud55c\ub2e4. \ub2e4\uc74c\uc740 \uc678\ubd80 \uba54\ubaa8\ub9ac\ub97c \ub458 \uacbd\uc6b0 \uac01 \ud540 \uc5ed\ud560\uc744 \uc815\ub9ac\ud55c \uac83\uc774\ub2e4.
 * \ud3ec\ud2b8 A\uc758 \ubd80\uac00\uae30\ub2a5
 PA7 : AD7(\uc678\ubd80 \uba54\ubaa8\ub9ac \uc778\ud130\ud398\uc774\uc2a4 \uc8fc\uc18c\uc640 \ub370\uc774\ud130 \ube44\ud2b8 7)
 PA6 : AD6(\uc678\ubd80 \uba54\ubaa8\ub9ac \uc778\ud130\ud398\uc774\uc2a4 \uc8fc\uc18c\uc640 \ub370\uc774\ud130 \ube44\ud2b8 6)
 PA5 : AD5(\uc678\ubd80 \uba54\ubaa8\ub9ac \uc778\ud130\ud398\uc774\uc2a4 \uc8fc\uc18c\uc640 \ub370\uc774\ud130 \ube44\ud2b8 5)
 PA4 : AD4(\uc678\ubd80 \uba54\ubaa8\ub9ac \uc778\ud130\ud398\uc774\uc2a4 \uc8fc\uc18c\uc640 \ub370\uc774\ud130 \ube44\ud2b8 4)
 PA3 : AD3(\uc678\ubd80 \uba54\ubaa8\ub9ac \uc778\ud130\ud398\uc774\uc2a4 \uc8fc\uc18c\uc640 \ub370\uc774\ud130 \ube44\ud2b8 3)
 PA2 : AD2(\uc678\ubd80 \uba54\ubaa8\ub9ac \uc778\ud130\ud398\uc774\uc2a4 \uc8fc\uc18c\uc640 \ub370\uc774\ud130 \ube44\ud2b8 2)
 PA1 : AD1(\uc678\ubd80 \uba54\ubaa8\ub9ac \uc778\ud130\ud398\uc774\uc2a4 \uc8fc\uc18c\uc640 \ub370\uc774\ud130 \ube44\ud2b8 1)
 PA0 : AD0(\uc678\ubd80 \uba54\ubaa8\ub9ac \uc778\ud130\ud398\uc774\uc2a4 \uc8fc\uc18c\uc640 \ub370\uc774\ud130 \ube44\ud2b8 0)<\/p>\n

 * \ud3ec\ud2b8 B(PB7 ~ PB0 : \ud540 10 ~ 17)
 – \ub0b4\ubd80 \ud480\uc5c5 \uc800\ud56d\uc774 \uc788\ub294 8\ube44\ud2b8 \uc591\ubc29\ud5a5 \uc785\ucd9c\ub825 \ub2e8\uc790\ub85c\uc11c, GPIO\ub85c \uc0ac\uc6a9\ub418\uc9c0 \uc54a\uc744 \uacbd\uc6b0\uc5d0\ub294 \ud0c0\uc774\uba38\/\uce74\uc6b4\ud130\ub098 SPI\uc6a9 \ub2e8\uc790 \ud639\uc740 PWM \ub2e8\uc790\ub85c\ub3c4 \uc0ac\uc6a9\ub41c\ub2e4. \ub2e4\uc74c\uc740 \ud2b9\uc218\uc6a9\ub3c4\ub85c \uc0ac\uc6a9\ub420 \uacbd\uc6b0 \ud3ec\ud2b8 B\uc758 \uac01 \ud540\uc758 \uae30\ub2a5\uc744 \uc815\ub9ac\ud55c \uac83\uc774\ub2e4.
 * \ud3ec\ud2b8 B\uc758 \ubd80\uac00\uae30\ub2a5
 PB7 : OC2\/OC1C(\ucd9c\ub825\ube44\uad50 \ub610\ub294 \ud0c0\uc774\uba38\/\uce74\uc6b4\ud1302\uc758 PWM \ucd9c\ub825, \ub610\ub294 \ucd9c\ub825\ube44\uad50\uc640 \ud0c0\uc774\uba38\/\uce74\uc6b4\ud1302\uc758  PWM\ucd9c\ub825 C)
PB6 : OC1B(\ucd9c\ub825\ube44\uad50 \ub610\ub294 \ud0c0\uc774\uba38\/\uce74\uc6b4\ud1301\uc758  PWM\ucd9c\ub825 B)
PB5 : OC1A(\ucd9c\ub825\ube44\uad50 \ub610\ub294 \ud0c0\uc774\uba38\/\uce74\uc6b4\ud1301\uc758 PWM \ucd9c\ub825 A)
PB4 : OC0(\ucd9c\ub825\ube44\uad50 \ub680\ub294 \ud0c0\uc774\uba38\/\uce74\uc6b4\ud1300\uc758 PWM \ucd9c\ub825)
PB3 : MISO(SPI \ubc84\uc2a4 \ub9c8\uc2a4\ud130 \uc785\ub825\/\uc885\uc18d \ucd9c\ub825)
PB2 : MOSI(SPI \ubc84\uc2a4 \ub9c8\uc2a4\ud130 \ucd9c\ub825\/\uc885\uc18d \uc785\ub825)
PB1 : SCK(SPI \ubc84\uc2a4 \uc9c1\ub82c \ud074\ub7ed)
PB0 : \/SS(SPI \uc885\uc18d \uc120\ud0dd \uc785\ub825)<\/p>\n

 * \ud3ec\ud2b8 C(PC7 ~ PC0 : \ud540 35 ~ 42)
 – \ub0b4\ubd80 \ud480\uc5c5 \uc800\ud56d\uc774 \uc788\ub294 8\ube44\ud2b8 \uc591\ubc29\ud5a5 \uc785\ucd9c\ub825 \ub2e8\uc790\ub85c\uc11c, \uc678\ubd80\uba54\ubaa8\ub9ac\ub97c \ub458 \uacbd\uc6b0\uc5d0\ub294 \uc8fc\uc18c\ubc84\uc2a4(A15 ~ A8)\ub85c \uc0ac\uc6a9\ub41c\ub2e4. \ub2e4\uc74c\uc740 \uc678\ubd80 \uba54\ubaa8\ub9ac\ub97c \ub458 \uacbd\uc6b0 \uac01 \ud540 \uc5ed\ud560\uc744 \uc815\ub9ac\ud55c \uac83\uc774\ub2e4.
 * \ud3ec\ud2b8 C\uc758 \ubd80\uac00\uae30\ub2a5
 PC7 : AD7(\uc678\ubd80 \uba54\ubaa8\ub9ac \uc778\ud130\ud398\uc774\uc2a4 \uc8fc\uc18c \ube44\ud2b8 15)
 PC6 : AD6(\uc678\ubd80 \uba54\ubaa8\ub9ac \uc778\ud130\ud398\uc774\uc2a4 \uc8fc\uc18c \ube44\ud2b8 14)
 PC5 : AD5(\uc678\ubd80 \uba54\ubaa8\ub9ac \uc778\ud130\ud398\uc774\uc2a4 \uc8fc\uc18c \ube44\ud2b8 13)
 PC4 : AD4(\uc678\ubd80 \uba54\ubaa8\ub9ac \uc778\ud130\ud398\uc774\uc2a4 \uc8fc\uc18c \ube44\ud2b8 12)
 PC3 : AD3(\uc678\ubd80 \uba54\ubaa8\ub9ac \uc778\ud130\ud398\uc774\uc2a4 \uc8fc\uc18c \ube44\ud2b8 11)
 PC2 : AD2(\uc678\ubd80 \uba54\ubaa8\ub9ac \uc778\ud130\ud398\uc774\uc2a4 \uc8fc\uc18c \ube44\ud2b8 10)
 PC1 : AD1(\uc678\ubd80 \uba54\ubaa8\ub9ac \uc778\ud130\ud398\uc774\uc2a4 \uc8fc\uc18c \ube44\ud2b8 9)
 PC0 : AD0(\uc678\ubd80 \uba54\ubaa8\ub9ac \uc778\ud130\ud398\uc774\uc2a4 \uc8fc\uc18c \ube44\ud2b8 8)<\/p>\n

 * \ud3ec\ud2b8 D(PD7 ~ PD0 : \ud540 25 ~32)
 – \ub0b4\ubd80 \ud480\uc5c5 \uc800\ud56d\uc774 \uc788\ub294 8\ube44\ud2b8 \uc591\ubc29\ud5a5 \uc785\ucd9c\ub825 \ub2e8\uc790\ub85c\uc11c, \ud0c0\uc774\uba38\uc6a9 \ub2e8\uc790 \ud639\uc740 \uc678\ubd80\uc778\ud130\ub7fd\ud2b8 \ub2e8\uc790\ub85c\ub3c4 \uc0ac\uc6a9\ub41c\ub2e4. \ub2e4\uc74c\uc740 \ud2b9\uc218\uc6a9\ub3c4\ub85c \uc0ac\uc6a9\ub420 \uacbd\uc6b0 \uac01 \ud540\uc758 \uae30\ub2a5\uc744 \uc815\ub9ac\ud55c \uac83\uc774\ub2e4.
 * \ud3ec\ud2b8 D\uc758 \ubd80\uac00\uae30\ub2a5
 PD7 : T2(\ud0c0\uc774\uba38\/\uce74\uc6b4\ud1302 \ud074\ub7ed \uc785\ub825)
 PD6 : T1(\ud0c0\uc774\uba38\/\uce74\uc6b4\ud1301 \ud074\ub7ed \uc785\ub825)
 PD5 : XCK1(USART1 \uc678\ubd80 \ud074\ub7ed \uc785\/\ucd9c\ub825)
 PD4 : IC1(\ud0c0\uc774\uba38\/\uce74\uc6b4\ud1301 \uc785\ub825 \ucea1\uccd0 \ud2b8\ub9ac\uac70)
 PD3 : INT3\/TXD1(\uc678\ubd80 \uc778\ud130\ub7fd\ud2b83 \uc785\ub825 \ub610\ub294 USART1 \uc804\uc1a1 \ud540)
 PD2 : INT2\/RXD1(\uc678\ubd80 \uc778\ud130\ub7fd\ud2b82 \uc785\ub825 \ub610\ub294 USART1 \uc218\uc2e0 \ud540)
 PD1 : INT1\/SDA(\uc678\ubd80 \uc778\ud130\ub7fd\ud2b81 \uc785\ub825 \ub610\ub294 TWI \uc9c1\ub82c \ub370\uc774\ud130)
 PD0 : INT0\/SCL(\uc678\ubd80 \uc778\ud130\ub7fd\ud2b80 \uc785\ub825 \ub610\ub294 TWI \uc9c1\ub82c \ud074\ub7ed)<\/p>\n

 * \ud3ec\ud2b8 E(PE7 ~ PE0 : \ud540 2 ~ 9)
 – \ub0b4\ubd80 \ud480\uc5c5 \uc800\ud56d\uc774 \uc788\ub294 8\ube44\ud2b8 \uc591\ubc29\ud5a5 \uc785\ucd9c\ub825 \ub2e8\uc790\ub85c\uc11c, \ud0c0\uc774\uba38\uc6a9 \ub2e8\uc790, \uc678\ubd80\uc778\ud130\ub7fd\ud2b8, \uc544\ub0a0\ub85c\uadf8 \ube44\uad50\uae30, USART\uc6a9 \ub2e8\uc790\ub85c\ub3c4 \uc0ac\uc6a9\ub41c\ub2e4. \ub2e4\uc74c\uc740 \ud2b9\uc218\uc6a9\ub3c4\ub85c \uc0ac\uc6a9\ub420 \uacbd\uc6b0 \uac01 \ud540\uc758 \uae30\ub2a5\uc744 \uc815\ub9ac\ud55c \uac83\uc774\ub2e4.
 * \ud3ec\ud2b8 E\uc758 \ubd80\uac00\uae30\ub2a5
 PE7 : INT7\/IC3(\uc678\ubd80 \uc778\ud130\ub7fd\ud2b8 7\uc785\ub825 \ub610\ub294 \ud0c0\uc774\uba38\/\uce74\uc6b4\ud1303 \uc785\ub825 \ucea1\uccd0 \ud2b8\ub9ac\uac70)
 PE6 : INT6\/T3(\uc678\ubd80 \uc778\ud130\ub7fd\ud2b8 6\uc785\ub825 \ub610\ub294 \ud0c0\uc774\uba38\/\uce74\uc6b4\ud1303 \ud074\ub7ed \uc785\ub825)
 PE5 : INT5\/OC3C(\uc678\ubd80 \uc778\ud130\ub7fd\ud2b8 5 \uc785\ub825 \ub610\ub294 \ud0c0\uc774\uba38\/\uce74\uc6b4\ud1303\uc758 \ucd9c\ub825 \ucc55\uccd0\uc640 PWM \ucd9c\ub825 C)
 PE4 : INT4\/OC3B(\uc678\ubd80 \uc778\ud130\ub7fd\ud2b8 4 \uc785\ub825 \ub610\ub294 \ud0c0\uc774\uba38 \uce74\uc6b4\ud130 3\uc758 \ucd9c\ub825 \ucc55\uccd0\uc640 PWM \ucd9c\ub825 B)
 PE3 : AIN1\/OC3A(\uc544\ub0a0\ub85c\uadf8 \ube44\uad50 \ubc18\ub300\uc785\ub825 \ub610\ub294 \ud0c0\uc774\uba38\/\uce74\uc6b4\ud1303\uc758 \ucd9c\ub825 \ube44\uad50\uc640 PWM \ucd9c\ub825 A)
 PE2 : AIN0\/XCK0(\uc544\ub0a0\ub85c\uadf8 \ube44\uad50 \uc785\ub825 \ub610\ub294 USART0 \uc678\ubd80 \ud074\ub7ed \uc785\/\ucd9c\ub825)
 PE1 : PD)\/TXD0(\ud504\ub85c\uadf8\ub7a8 \ub370\uc774\ud130 \ucd9c\ub825 \ub610\ub294 UART0 \uc804\uc1a1 \ud540)
 PE2 : PDI\/RXD0(\ud504\ub85c\uadf8\ub7a8 \ub370\uc774\ud130 \uc785\ub825 \ub610\ub294 UART0 \uc218\uc2e0 \ud540)<\/p>\n

 * \ud3ec\ud2b8 F(PF7 ~ PF0 : \ud540 54 ~ 61)
 – \ub0b4\ubd80 \ud480\uc5c5 \uc800\ud56d\uc774 \uc788\ub294 8\ube44\ud2b8 \uc591\ubc29\ud5a5 \uc785\ucd9c\ub825 \ub2e8\uc790\ub85c\uc11c, AD\ubcc0\ud658\uae30 \ud639\uc740 JTAG \uc778\ud130\ud398\uc774\uc2a4\uc6a9 \ub2e8\uc790\ub85c\ub3c4 \uc0ac\uc6a9\ub41c\ub2e4. \ub2e4\uc74c\uc740 AD \ubcc0\ud658\uc774\ub098, JTAG\uc6a9\ub3c4\ub85c \uc0ac\uc6a9\ub420 \uacbd\uc6b0\uc758 \uac01 \ud540 \uc5ed\ud560\uc744 \uc815\uc758\ud55c \uac83\uc774\ub2e4.
 * \ud3ec\ud2b8 F\uc758 \ubd80\uac00\uae30\ub2a5
 PF7 : ADC7\/TDI(ADC \uc785\ub825 \ucc44\ub110 7 \ub610\ub294 JTAG Test Data Input)
 PF6 : ADC6\/TDO(ADC \uc785\ub825 \ucc44\ub110 6 \ub610\ub294 JTAG Test Data Output)
 PF5 : ADC5\/TMS(ADC \uc785\ub825 \ucc44\ub110 5 \ub610\ub294 JTAG Test Mode Select)
 PF4 : ADC4\/TCK(ADC \uc785\ub825 \ucc44\ub110 4 \ub610\ub294 JTAG Test Clock)
 PF3 : ADC3(ADC \uc785\ub825 \ucc44\ub110 3)
 PF2 : ADC2(ADC \uc785\ub825 \ucc44\ub110 2)
 PF1 : ADC1(ADC \uc785\ub825 \ucc44\ub110 1)
 PF0 : ADC0(ADC \uc785\ub825 \ucc44\ub110 0)<\/p>\n

 * \ud3ec\ud2b8 G(PG4 ~ PG0, \ud540 19, 18, 43, 34, 33)
 – \ub0b4\ubd80 \ud480\uc5c5 \uc800\ud56d\uc774 \uc788\ub294 8\ube44\ud2b8 \uc591\ubc29\ud5a5 \uc785\ucd9c\ub825 \ub2e8\uc790\ub85c\uc11c, \uc678\ubd80 \uba54\ubaa8\ub9ac \uc811\uc18d\uc744 \uc704\ud55c \uc2a4\ud2b8\ub85c\ube0c \uc2e0\ud638\uc6a9, RTC(Real Time Counter) \ud0c0\uc774\uba38\uc6a9 \ubc1c\uc9c4\uae30 \ub2e8\uc790\ub85c\ub3c4 \uc0ac\uc6a9\ub41c\ub2e4.
 * \ud3ec\ud2b8 G\uc758 \ubd80\uac00\uae30\ub2a5
 PG4 : TOSC1(RTC \uc624\uc2e4\ub808\uc774\ud130 \ud0c0\uc774\uba38\/\uce74\uc6b4\ud130 0)
 PG3 : TOSC2(RTC \uc624\uc2e4\ub808\uc774\ud130 \ud0c0\uc774\uba38\/\uce74\uc6b4\ud130 0)
 PG2 : ALE(\uc678\ubd80\uba54\ubaa8\ub9ac\uc5d0 \uc8fc\uc18c \ub798\uce58 \uc778\uc5d0\uc774\ube14)
 PG1 : RD(\uc678\ubd80\uba54\ubaa8\ub9ac\uc5d0 \uc2a4\ud2b8\ub85c\ube0c \uc77d\uae30)
 PG0 : WR(\uc678\ubd80\uba54\ubaa8\ub9ac\uc5d0 \uc2a4\ud2b8\ub85c\ube0c \uc4f0\uae30)<\/p>\n","protected":false},"excerpt":{"rendered":"

 * AVR \ub9c8\uc774\ud06c\ub85c\ucee8\ud2b8\ub864\ub7ec \uc785\ucd9c\ub825 \ud3ec\ud2b8 \ud2b9\uc9d5  – 6\uac1c\uc758 8\ube44\ud2b8 I\/O \ud3ec\ud2b8\uc640 1\uac1c\uc758 5\ube44\ud2b8 I\/O \ud3ec\ud2b8\ub85c \uad6c\uc131\ub418\uc5b4 \uc788\ub2e4. – \ucd9c\ub825\ud3ec\ud2b8\uc758 \ubc84\ud37c\ub294 \ub9ce\uc740 \uc720\uc785\uc804\ub958\uc640 \uc720\ucd9c\uc804\ub958\ub97c \uc0ac\uc6a9(\ucd5c\ub300 40mA)\ud560 \uc218 \uc788\ub2e4. – \ubaa8\ub4e0 \ud3ec\ud2b8 \ud540\uc740 \uac1c\ubcc4\uc801\uc73c\ub85c \ub0b4\ubd80 \ud480\uc5c5 \uc800\ud56d\uc744 \uc0ac\uc6a9\ud560 \uc218 \uc788\ub2e4. – \ubaa8\ub4e0 I\/O\ud540\uc740 VCC\uc640 GND … Continue reading →<\/span><\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":[],"categories":[21],"tags":[106,112,208,707],"_links":{"self":[{"href":"http:\/\/pchero21.com\/index.php?rest_route=\/wp\/v2\/posts\/615"}],"collection":[{"href":"http:\/\/pchero21.com\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"http:\/\/pchero21.com\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"http:\/\/pchero21.com\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"http:\/\/pchero21.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=615"}],"version-history":[{"count":0,"href":"http:\/\/pchero21.com\/index.php?rest_route=\/wp\/v2\/posts\/615\/revisions"}],"wp:attachment":[{"href":"http:\/\/pchero21.com\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=615"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"http:\/\/pchero21.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=615"},{"taxonomy":"post_tag","embeddable":true,"href":"http:\/\/pchero21.com\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=615"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}