{"id":614,"date":"2008-09-08T15:30:44","date_gmt":"2008-09-08T15:30:44","guid":{"rendered":"http:\/\/pchero21.com\/?p=614"},"modified":"2008-09-08T15:30:44","modified_gmt":"2008-09-08T15:30:44","slug":"atmega128-%ed%95%80-%ea%b8%b0%eb%8a%a5","status":"publish","type":"post","link":"http:\/\/pchero21.com\/?p=614","title":{"rendered":"ATMega128 \ud540 \uae30\ub2a5."},"content":{"rendered":"<p><P><br \/>&nbsp;&#8211; RESET(\ud54020) : \uc785\ub825\ub2e8\uc790\ub85c &#8216;0&#8217; \ub808\ubca8\uc774 \uc785\ub825\ub418\uba74 \ub9ac\uc14b\ub418\uc5b4 PC(Program Counter)\ub294 \uc77c\ubc18\uc801\uc73c\ub85c 0\ubc88\uc9c0\ub97c \uac00\ub974\ud0a4\uace0 0\ubc88\uc9c0\ubd80\ud130 \ud504\ub85c\uadf8\ub7a8\uc774 \uc2dc\uc791\ub41c\ub2e4. \ub9ac\uc14b\uc2dc \ub300\ubd80\ubd84\uc758 \ub808\uc9c0\uc2a4\ud130\ub294 \ucd08\uae30\ud654\ub41c\ub2e4.<br \/>&nbsp;&#8211; XTAL1, XTAL2(\ud54024, 23) : \ubc1c\uc9c4\uc6a9 \uc99d\ud3ed\uae30 \uc785\ub825 \ubc0f \ucd9c\ub825 \ub2e8\uc790.<br \/>&nbsp;&#8211; Vcc(\ud54021, 51) : \uc804\uc6d0 \uc785\ub825 \ub2e8\uc790<br \/>&nbsp;&#8211; GND(\ud54022, 53, 63) : \uadf8\ub77c\uc6b4\ub4dc \uc785\ub825 \ub2e8\uc790.<br \/>&nbsp;&#8211; AVCC(\ud540 64) : AD\ubcc0\ud658\uae30 \ubc0f \ud3ec\ud2b8 F\uc5d0 \ub300\ud55c \uacf5\uae09 \uc804\uc555<br \/>&nbsp;&#8211; AREF(\ud540 62) : ADC \ucc38\uc870 \uc804\uc555(Reference Voltage)<br \/>&nbsp;&#8211; PEN(\ud5401) : SPI\ub97c \ud65c\uc131\ud654\uc2dc\ud0a4\ub294 \ub2e8\uc790\ub85c \uc77c\ubc18\uc801\uc778 \ub3d9\uc791\ubaa8\ub4dc\uc5d0\uc11c\ub294 \uc0ac\uc6a9\ud558\uc9c0 \uc54a\uace0 \ud30c\uc6cc \uc628 \ub9ac\uc14b\uc2dc 0\uc0c1\ud0dc\ub85c \uc720\uc9c0\ud574 SPI\ub97c \ud5c8\uc6a9\ud558\uac8c \ud55c\ub2e4.<br \/>&nbsp;&#8211; \ud3ec\ud2b8A(PA7 ~ PA0 : \ud540 44-51) : \ub0b4\ubd80 \ud480\uc5c5 \uc800\ud56d\uc774 \uc788\ub294 8\ube44\ud2b8 \uc591\ubc29\ud5a5 \uc785\ucd9c\ub825 \ub2e8\uc790. \uc678\ubd80 \uba54\ubaa8\ub9ac\ub97c \ub458 \uacbd\uc6b0\uc5d0\ub294 \uc8fc\uc18c\ubc84\uc2a4(A7-A0)\uc640 \ub370\uc774\ud130\ubc84\uc2a4(D7-D0)\ub85c \uc0ac\uc6a9.<br \/>&nbsp;&#8211; \ud3ec\ud2b8B(PB7 ~ PB0 : \ud540 10-17) : \ub0b4\ubd80 \ud480\uc5c5 \uc800\ud56d\uc774 \uc788\ub294 8\ube44\ud2b8 \uc591\ubc29\ud5a5 \uc785\ucd9c\ub825 \ub2e8\uc790. SPI\uc6a9 \ub2e8\uc790 \ud639\uc740 PWM\ub2e8\uc790\ub85c\ub3c4 \uc0ac\uc6a9\ub41c\ub2e4.<br \/>&nbsp;&#8211; \ud3ec\ud2b8C(PC7 ~ PC0 : \ud540 35-42) : \ub0b4\ubd80 \ud480\uc5c5 \uc800\ud56d\uc774 \uc788\ub294 8\ube44\ud2b8 \uc591\ubc29\ud5a5 \uc785\ucd9c\ub825 \ub2e8\uc790. \uc678\ubd80\uba54\ubaa8\ub9ac\ub97c \ub458 \uacbd\uc6b0\uc5d0\ub294 \uc8fc\uc18c\ubc84\uc2a4(A15-A8)\ub85c \uc0ac\uc6a9\ub41c\ub2e4.<br \/>&nbsp;&#8211; \ud3ec\ud2b8D(PD7 ~ PD0 : \ud540 25-32) : \ub0b4\ubd80 \ud480\uc5c5 \uc800\ud56d\uc774 \uc788\ub294 8\ube44\ud2b8 \uc591\ubc29\ud5a5 \uc785\ucd9c\ub825 \ub2e8\uc790. \ud0c0\uc774\uba38\uc6a9 \ub2e8\uc790 \ud639\uc740 \uc678\ubd80\uc785\ud130\ub7fd\ud2b8\uc6a9 \ub2e8\uc790\ub85c\ub3c4 \uc0ac\uc6a9\ub41c\ub2e4.<br \/>&nbsp;&#8211; \ud3ec\ud2b8E(PE7 ~ PE0 : \ud540 2-9) : \ub0b4\ubd80 \ud480\uc5c5 \uc800\ud56d\uc774 \uc788\ub294 8\ube44\ud2b8 \uc591\ubc29\ud5a5 \uc785\ucd9c\ub825 \ub2e8\uc790. \ud0c0\uc774\uba38\uc6a9 \ub2e8\uc790, \uc678\ubd80 \uc778\ud130\ub7fd\ud2b8, \uc544\ub0a0\ub85c\uadf8 \ube44\uad50\uae30, USART\uc6a9 \ub2e8\uc790\ub85c\ub3c4 \uc0ac\uc6a9\ub41c\ub2e4.<br \/>&nbsp;&#8211; \ud3ec\ud2b8F(PF7 ~ PF0 : \ud540 54-61) : \ub0b4\ubd80 \ud480\uc5c5 \uc800\ud56d\uc774 \uc788\ub294 5\ube44\ud2b8 \uc591\ubc29\ud5a5 \uc785\ucd9c\ub825 \uac04\uc790. AD \ubcc0\ud658\uae30 \ud639\uc740 JTAG \uc778\ud130\ud398\uc774\uc2a4\uc6a9 \ub2e8\uc790\ub85c\ub3c4 \uc0ac\uc6a9\ub41c\ub2e4.<br \/>&nbsp;&#8211; \ud3ec\ud2b8G(PG4~PG0 : \ud540 19, 18, 43, 34, 33) : \ub0b4\ubd80 \ud480\uc5c5 \uc800\ud56d\uc774 \uc788\ub294 8\ube44\ud2b8 \uc591\ubc29\ud5a5 \uc785\ucd9c\ub825 \ub2e8\uc790. \uc678\ubd80 \uba54\ubaa8\ub9ac \uc811\uc18d\uc744 \uc704\ud55c \uc2a4\ud2b8\ub85c\ube0c \uc2e0\ud638\uc6a9, RTC(Real Time Counter) \ud0c0\uc774\uba38\uc6a9 \ubc1c\uc9c4\uae30 \ub2e8\uc790\ub85c\ub3c4 \uc0ac\uc6a9\ub41c\ub2e4.<\/p>\n<p>&nbsp;<br \/>&nbsp;ATmega128 \ud3ec\ud2b8\uc640 \ud540 : \uc785\ucd9c\ub825 \ud3ec\ud2b8(I\/O) \ubcc4 \uc124\uba85<\/p>\n<p>\uae30\ub2a5\uad6c\ubd84 : \ud540 \uc774\ub984 : \ud540 \ubc88\ud638 : \ud540 \uba85\uce6d : \uae30\ub2a5<br \/>================================================================================================<br \/>\uae30\ub2a5 : I\/O \ub610\ub294 Address<br \/>\ud540 \uc774\ub984 : PA0(AD0) ~ PA7(AD7)<br \/>\ud540 \ubc88\ud638 : 51 ~ 44<br \/>\ud540 \uba85\uce6d : PortA<br \/>\uae30\ub2a5 : <br \/>[PA0 ~ PA7 \uc73c\ub85c \uc0ac\uc6a9] \uc77c\ubc18 \ubc94\uc6a9 I\/O\ub85c \uc0ac\uc6a9\uc2dc \uc2e0\ud638 \ubc29\ud5a5(DDRA), \ucd9c\ub825\ub420 \ub370\uc774\ud130 \uc800\uc7a5(PORTA), \uc785\ub825\ub41c \ub370\uc774\ud130 \uc800\uc7a5(PINA) 3\uac1c\uc758 \ub808\uc9c0\uc2a4\ud130 \uc124\uc815\uc744 \ud1b5\ud574 \uc81c\uc5b4\ub418\ub294 \uc591\ubc29\ud5a5 \ubc94\uc6a9 I\/O (GPIO) \ud3ec\ud2b8\ub85c \uc0ac\uc6a9.<br \/>[AD0 ~ AD7 \uc73c\ub85c \uc0ac\uc6a9] \uc678\ubd80 \uba54\ubaa8\ub9ac\ub97c \uc811\uadfc\ud558\uae30 \uc704\ud574 \uc0ac\uc6a9 \ub420 \ub54c\ub294 \ud558\uc704 \uc5b4\ub4dc\ub808\uc2a4 \ubc84\uc2a4\ub85c \uc0ac\uc6a9, ALE \uc2e0\ud638\uc5d0 \uc758\ud574 \uc0c1\uc704 \uc5b4\ub4dc\ub808\uc2a4\uc640 \ubd84\ub9ac.<br \/>================================================================================================<br \/>\uae30\ub2a5 : I\/O<br \/>\ud540 \uc774\ub984 : PB0 ~ PB7<br \/>\ud540 \ubc88\ud638 : 10 ~ 17<br \/>\ud540 \uba85\uce6d : PortB<br \/>\uae30\ub2a5 : [PB0 ~ PB7 \uc73c\ub85c \uc0ac\uc6a9] Port A \uc640 \ub9c8\ucc2c\uac00\uc9c0\ub85c DDRB, PORTB, PINB \ub808\uc9c0\uc2a4\ud130\ub4e4\uc5d0 \uc758\ud574 \uc81c\uc5b4\ub418\ub294 \uc591\ubc29\ud5a5 \ubc94\uc6a9 I\/O \ud3ec\ud2b8\ub85c \uc0ac\uc6a9<br \/>[\ub2e4\ub978 \uc6a9\ub3c4\ub85c \uc0ac\uc6a9\ub420 \ub54c] Port A \uc640\ub294 \ub2ec\ub9ac \uac01 \ud540\ub9c8\ub2e4 \uc11c\ub85c \ub2e4\ub978 \uc6a9\ub3c4 (PWM \ucd9c\ub825, SPI\ub85c \uc0ac\uc6a9)<br \/>================================================================================================<br \/>\uae30\ub2a5 :&nbsp; I\/O \ub610\ub294 Address<br \/>\ud540 \uc774\ub984 : PC0(A8) ~ PC7(A15)<br \/>\ud540 \ubc88\ud638 : 35 ~ 42<br \/>\ud540 \uba85\uce6d : PortC<br \/>\uae30\ub2a5 : [PC0 ~ PC7\uc73c\ub85c \uc0ac\uc6a9] DDEC, PORTC, PINC \ub808\uc9c0\uc2a4\ud130\ub4e4\uc5d0 \uc758\ud574 \uc81c\uc5b4\ub418\ub294 \uc57c\ubc29\ud5a5 \ubc94\uc6a9 I\/O \ud3ec\ud2b8\ub85c \uc0ac\uc6a9.<br \/>[A8 ~ A15 \uc73c\ub85c \uc0ac\uc6a9] \uc678\ubd80 \uba54\ubaa8\ub9ac\ub97c \uc811\uadfc\ud558\uae30 \uc704\ud574 \uc0ac\uc6a9\ub420 \uc218 \uc788\uc73c\uba70, Port A \uac00 \ud558\uc704 \uc5b4\ub4dc\ub808\uc2a4\ubc84\uc2a4\ub85c \uc0ac\uc6a9\ub41c \uac83\uacfc \ub2ec\ub9ac Port C \ub294 \uc0c1\uc704 \uc5b4\ub4dc\ub808\uc2a4 \ubc84\uc2a4\ub85c \uc0ac\uc6a9\ub428<br \/>================================================================================================<br \/>\uae30\ub2a5 : I\/O<br \/>\ud540 \uc774\ub984 : PD0 ~ PD7<br \/>\ud540 \ubc88\ud638 : 25 ~ 32<br \/>\ud540 \uba85\uce6d : PortD<br \/>\uae30\ub2a5 : [PD0 ~ PD7 \uc73c\ub85c \uc0ac\uc6a9] DDRD, PORTD, PIND \ub808\uc9c0\uc2a4\ud130\ub4e4\uc5d0 \uc758\ud574 \uc81c\uc5b4\ub418\ub294 \uc591\ubc29\ud5a5 \ubc94\uc6a9 I\/O \ud3ec\ud2b8\ub85c \uc0ac\uc6a9<br \/>[\ub2e4\ub978 \uc6a9\ub3c4\ub85c \uc0ac\uc6a9\ub420 \ub54c] \uac01 \ud540\ub9c8\ub2e4 \uc11c\ub85c \ub2e4\ub978 \uc6a9\ub3c4(Timer, USART, TWI)\ub85c \uc0ac\uc6a9<br \/>================================================================================================<br \/>\uae30\ub2a5 : I\/O<br \/>\ud540 \uc774\ub984 : PE0 ~ PE7<br \/>\ud540 \ubc88\ud638 : 2 ~ 9<br \/>\ud540 \uba85\uce6d : PortE<br \/>\uae30\ub2a5 : [PE0 ~ PE7 \uc73c\ub85c \uc0ac\uc6a9] DDRE, PORTE, PINE \ub808\uc9c0\uc2a4\ud130\ub4e4\uc5d0 \uc758\ud574 \uc81c\uc5b4\ub418\ub294 \uc591\ubc29\ud5a5 \ubc94\uc6a9 I\/O \ud3ec\ud2b8\ub85c \uc0ac\uc6a9.<br \/>[\ub2e4\ub978 \uc6a9\ub3c4\ub85c \uc0ac\uc6a9\ub420 \ub54c] \uac01 \ud540\ub9c8\ub2e4 \uc11c\ub85c \ub2e4\ub978 \uc6a9\ub3c4(Timer, USART)\ub85c \uc0ac\uc6a9<br \/>================================================================================================<br \/>\uae30\ub2a5 : I\/O \ub610\ub294 ADC<br \/>\ud540 \uc774\ub984 : PF0(ADC0) ~ PF7(ADC7)<br \/>\ud540 \ubc88\ud638 : 61 ~ 54<br \/>\ud540 \uba85\uce6d : PortF<br \/>\uae30\ub2a5 : [PF0 ~ PF7 \uc73c\ub85c \uc0ac\uc6a9] DDRF, PORTF, PINF \ub808\uc9c0\uc2a4\ud130\ub4e4\uc5d0 \uc758\ud574 \uc81c\uc5b4\ub418\ub294 \uc591\ubc29\ud5a5 \ubc94\uc6a9 I\/O \ud3ec\ud2b8\ub85c \uc0ac\uc6a9.<br \/>[ADC0 ~ ADC7 \uc73c\ub85c \uc0ac\uc6a9] ATmega128 \ub0b4\ubd80\uc5d0 \uc788\ub294 8\ucc44\ub110(0~7)\uc758 10-bit ADC\uc758 \uc544\ub0a0\ub85c\uadf8 \uc785\ub825\uc73c\ub85c \uc0ac\uc6a9<br \/>================================================================================================<br \/>\uae30\ub2a5 : I\/O<br \/>\ud540 \uc774\ub984 : PG0 ~ PG4<br \/>\ud540 \ubc88\ud638 : 33, 34, 43, 18, 19<br \/>\ud540 \uba85\uce6d : PortG<br \/>\uae30\ub2a5 : [PG0 ~ PG7 \uc73c\ub85c \uc0ac\uc6a9\ub420 \ub54c] DDRG, PORTG, PING \ub808\uc9c0\uc2a4\ud130\ub4e4\uc5d0 \uc758\ud574 \uc81c\uc5b4\ub418\ub294 \uc591\ubc29\ud5a5 \ubc94\uc6a9 I\/O \ud3ec\ud2b8\ub85c \uc0ac\uc6a9.<br \/>[\ub2e4\ub978 \uc6a9\ub3c4\ub85c \uc0ac\uc6a9\ub420 \ub54c] \uac01 \ud540\ub9c8\ub2e4 \uc11c\ub85c \ub2e4\ub978 \uc6a9\ub3c4(Timer, \uc678\ubd80 \uba54\ubaa8\ub9ac I\/F \uc81c\uc5b4\uc2e0\ud638)\ub85c \uc0ac\uc6a9<br \/>================================================================================================<br \/><\/P><\/p>\n","protected":false},"excerpt":{"rendered":"<p>&nbsp;&#8211; RESET(\ud54020) : \uc785\ub825\ub2e8\uc790\ub85c &#8216;0&#8217; \ub808\ubca8\uc774 \uc785\ub825\ub418\uba74 \ub9ac\uc14b\ub418\uc5b4 PC(Program Counter)\ub294 \uc77c\ubc18\uc801\uc73c\ub85c 0\ubc88\uc9c0\ub97c \uac00\ub974\ud0a4\uace0 0\ubc88\uc9c0\ubd80\ud130 \ud504\ub85c\uadf8\ub7a8\uc774 \uc2dc\uc791\ub41c\ub2e4. \ub9ac\uc14b\uc2dc \ub300\ubd80\ubd84\uc758 \ub808\uc9c0\uc2a4\ud130\ub294 \ucd08\uae30\ud654\ub41c\ub2e4.&nbsp;&#8211; XTAL1, XTAL2(\ud54024, 23) : \ubc1c\uc9c4\uc6a9 \uc99d\ud3ed\uae30 \uc785\ub825 \ubc0f \ucd9c\ub825 \ub2e8\uc790.&nbsp;&#8211; Vcc(\ud54021, 51) : \uc804\uc6d0 \uc785\ub825 \ub2e8\uc790&nbsp;&#8211; GND(\ud54022, 53, 63) : &hellip; <a href=\"http:\/\/pchero21.com\/?p=614\">Continue reading <span class=\"meta-nav\">&rarr;<\/span><\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":[],"categories":[21],"tags":[106,112],"_links":{"self":[{"href":"http:\/\/pchero21.com\/index.php?rest_route=\/wp\/v2\/posts\/614"}],"collection":[{"href":"http:\/\/pchero21.com\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"http:\/\/pchero21.com\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"http:\/\/pchero21.com\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"http:\/\/pchero21.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=614"}],"version-history":[{"count":0,"href":"http:\/\/pchero21.com\/index.php?rest_route=\/wp\/v2\/posts\/614\/revisions"}],"wp:attachment":[{"href":"http:\/\/pchero21.com\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=614"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"http:\/\/pchero21.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=614"},{"taxonomy":"post_tag","embeddable":true,"href":"http:\/\/pchero21.com\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=614"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}